Design for Testability (DFT)

Tests & reviews play pivotal importance in electronic component creations, undoubtedly. The plan details need to be looked up first-hand, as it eliminates the need for further configuration changes and additional investments in terms of time and money.

Team TrovaSemi, with its unique expertise in Design for Test services, works closely with the client to cater services ranging from DFT Architecture to Post silicon support. With a plethora of successful DFT projects to name in all work modes, here at TrovaSemi, the expertise lies in ultra-sophisticated technical skill set and hands-on experience overall leading to highly efficient EDA tools.

Our Key Offerings

DFT Architecture and Implementation

• Flow and Methodology Development

ATPG Pattern Generation for Different Fault Models

• ATPG Pattern Generation for Stuck-at, Transition, Bridging, and Cell aware Fault Model and Extensive Coverage Analysis at Block Level and SOC Level.
• Low Power Pattern Generation, Pattern Optimization, and TPI Analysis.
• Pattern Retargeting at SOC Level.

Scan Implementation with and without Compression

• Implementation of Hierarchical and Flat Scan for Small and Multi-million Gates Design.
• LBIST Implementation and Spyglass at RTL Level.
• LEC for Scan Netlist.
• IJTAG Implementation at Block and SOC Level.

IO Testing using JTAG/BSCAN Implementation

• Implementation of Boundary Scan at SOC Level.
• Expertise in IEEE1149.1 and IEEE1149.6 Standards.

DFT Validation

• Simulations at Timing and No-timing.
• DFX Validation at RTL and Gate Level.
• Analog BIST Simulations.

Post Silicon Debug and ATE Support

• Post Silicon Support and ATE Bring up.
• ATE Board Design and Bring up.
• Test Program Development and Testing in different types of testers like Advantest 93K and Production support.