Job Description :

• BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred.
• Prior experience in timing and or RTL design of high-speed interfaces.
• Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs.
• Knowledge of the IP/SoC level timing closure flow and methodology.
• Strong command of Verilog/System Verilog language.
• Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies.
• Ability to handle multiple projects/tasks successfully.
• Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow.
• Hands-on experience in timing constraints generation and management.
• Proficiency in scripting languages (TCL and Perl).
• Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools.
• Capability to understand and implement improvements to existing methodologies and flows.
• Strong background in Constraint analysis and debugging, using industry-standard tools.
• Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing.
• Team player with a passion for innovating and a can-do attitude.
• Self-starter and highly motivated.

Desired Skills :

• Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs.
• Experience designing or integrating IP.
• Experience in high-speed and low-power digital design using advanced deep-micron processes.
• Experience with highly configurable designs