Job Description :

• Full-chip DFT working experience with multiple design Tape Outs.
• Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements.
• Expertise in Scan Compression(EDT/OPMISR+), MBIST, BSCAN, ATPG implementation and verification.
• Hands-on Experience with industry-standard DFT EDA tools and flows.
• Good Knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments and LEC.
• Excellent problem-solving and debugging skills. Proactive in nature.
• Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies and processes.
• Leading junior teams, Mentoring/Training and Project leadership.
• Excellent Customer interaction, Communication and Teamwork skills.

Desired Skills :

• ATPG (at-speed and stuck-at), At Speed Scan, Design for Testability (DFT).