Job Description :

• Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes.
• Must-Have – Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning.
• Hands-on experience in IO Planning, Bump Plan and RDL Routing.
• Experience in ECOs, Synthesis and STA, and Power analysis.
• Hands-on experience in Physical verification.
• Hands-on experience on 7nm and 10nm technology nodes.
• Good-to-Have Effective communication skills to interact with cross-functional teams.
• Good problem-solving skills.
• Good Scripting skills.